During the process of designing of integrated circuits, there may be instances where the same power supply pad may need to provide a supply voltage to many different circuit blocks through conductive pathways or interconnections. Each circuit block may have particular current and/or resistance specifications. That is, each circuit block may require a particular amount of current, or be able to tolerate only a particular amount of voltage drop from the power supply pad, or both so that a maximum interconnection resistance may be determined.
In a typical integrated circuit fabrication process, various different metal layers may be available for use by the designer to form such conductive pathways. The thickness and resistivity of these metal layers may be fixed for a given process, but the designer may still control the length and width of each of the pathways. The pathways may comprise multiple interconnected portions. Connections from one metal layer to another may be formed through vias or other structures, as may be known in the art.
A great deal of manual design work may be needed to define the individual geometric routes for the conductive interconnections needed between power supply pads and circuit blocks. Each of these routes is non-shared, e.g., electrically non-overlapping, with any other route on the same network in a design, to meet strict voltage and resistance requirements. This type of routing is generally known as star routing. In so-called Manhattan-type routing, each route comprises metal runs that connect only directly or at right angles. Each conductive pathway may have a different fabrication layer and width control requirement.
There are many difficulties with the conventional routing methodology presently used by integrated circuit designers. First, the present methodology is manual, and manual routing is a very tedious and labor intensive job. The designer must manually determine the routes from each power supply pad to each connected circuit block while considering all relevant design constraints. Since no sharing of any conductive path portions is allowed between the different routes in star routing, the designer must take extra care while allocating the routing resources.
Further, for each change in a design floorplan, e.g., placement of power supply pads and circuit blocks, the routing may need to be repeated, with no gain in designer productivity. Additionally, changes to circuit block power requirements may also require changes to the width and/or length of each of the various conductive pathways. Modification of circuit block power requirements is a common occurrence during design iterations, and may also dictate a complete reworking of an initial routing.
There is also presently no automatic validation option available to verify the routing results. Logically, the various conductive paths are all the same, therefore traditional connectivity extraction tools used for layout versus schematic verification and electrical rule checking will not flag the paths as having any violations. That is, forbidden electrical overlaps that may occur may not necessarily cause noticeable topology problems, but they may still adversely impact circuit operation due to the stringent voltage and resistance requirements.
Finally, conventional automated routing tools currently available from commercial electronic design tool vendors route the entire integrated circuit as a whole. Thus, there may be no provision in any of them to separately create multiple non-shared interconnections on the same network, e.g., route a selected subset of an integrated circuit. This limitation may interfere with design re-use, further constraining circuit designer productivity.
Thus, there is a need for an improved approach to automating the design and routing of non-shared one-to-many conductive pathways between a common pad and circuit blocks in an integrated circuit. Accordingly, the inventors have developed a novel way to help circuit designers and design tool vendors address this issue.